Jump on condition instructions specify a jump to a specified address if a condition is met.
The condition is specified by the condition code bits in the status register.
8-bit argument numbers are extended to 16-bits using Sign extension.
The 8-bit argument becomes the least significant byte
The higher byte is extended with ones or zeros.
Positive arguments have the higher byte extended with zeros
Nnegative numbers are extended with ones with the argument in 2βs complement form.
βββββββββββββββββββββββββββ
These instructions manipulate single bits within the working and STS registers.
Instruction structure:
15 7 6 3 0
ββββββββββββ¬ββββββββ¬ββββ
β bit op β bn βdr β
ββββββββββββ΄ββββββββ΄ββββ
Bit operation:
Bits 11-15 are always set to one for a bit operation.
Bits 7-10 determine the type of operation as follows:
ββββββββββββ¬βββββββββββββ¬ββββββββββββββββββββββββββββββββ¬ββββββββββββββ
βtype bits β mnemonic β description β code β
β10 9 8 7 β β β β
ββββββββββββΌβββββββββββββΌββββββββββββββββββββββββββββββββΌββββββββββββββ€
β 0 0 0 0 β BSET ZRO β bit β΅ 0 β 174000β β
β 0 0 0 1 β BSET ONE β bit β΅ 1 β 174200β β
β 0 0 1 0 β BSET BCM β bit β΅ bit β 174400β β
β 0 0 1 1 β BSET BAC β bit β΅ K β 174600β β
β 0 1 0 0 β BSKP ZRO β skip if bit = 0 β 175000β β
β 0 1 0 1 β BSKP ONE β skip if bit = 1 β 175200β β
β 0 1 1 0 β BSKP BCM β skip if bit = bit β 175400β β
β 0 1 1 1 β BSKP BAC β skip if bit = K β 175600β β
β 1 0 0 0 β BSTC β bit β΅ K, K β΅ 1 β 176000β β
β 1 0 0 1 β BSTA β bit β΅ K, K β΅ 0 β 176200β β
β 1 0 1 0 β BLDC β K β΅ bit β 176400β β
β 1 0 1 1 β BLDA β K β΅ bit β 176600β β
β 1 1 0 0 β BANC β K β΅ (bit AND K) β 177000β β
β 1 1 0 1 β BAND β K β΅ (bit AND K) β 177200β β
β 1 1 1 0 β BORC β K β΅ (bit OR K) β 177400β β
β 1 1 1 1 β BORA β K β΅ (bit OR K) β 177600β β
ββββββββββββ΄βββββββββββββ΄ββββββββββββββββββββββββββββββββ΄ββββββββββββββ
Sub-instructions:
Only the BSET and BSKP instructions have the following qualifying sub-instructions:
ZRO
ONE
BCM
BAC
bn (bits 3-6):
The address of the bit to be manipulated is given by these four bits.
Remember that each bit is given its OCTAL address.
dr (bits 0-2):
The following registers allow bit operations and are specified as follows:
ββββββββββββ¬βββββββββββ¬βββββββββ
β register β mnemonic β code β
ββββββββββββΌβββββββββββΌβββββββββ€
β STS β β β 0β β
β D β DD β 1β β
β P β DP β 2β β
β B β DB β 3β β
β L β DL β 4β β
β A β DA β 5β β
β T β DT β 6β β
β X β DX β 7β β
ββββββββββββ΄βββββββββββ΄βββββββββ
β For STS no mnemonic is required as it is implied by the following table of compound mnemonics:
STS register:
There are only eight bits which can be operated on in the STS register. They have special mnemonics and unique octal code values which combine the bn and dr fields.
These instructions address single bytes within the memory map.
A special addressing mode is used for these instructions, utilizing the T and X registers.
The contents of T point to the beginning of a character string, and the contents of X point to a specific byte within that string.
Two 16-bit words (D1 and D2) specify the operands used in decimal instructions.
D1: The first descriptor gives the word address of the decimal operand in memory.
D2: Describes the following operand features:
lr (bit 15):
lr = 0: The operand starts in the left byte of a memory word (least significant 8 bits).
lr = 1: The operand starts in the right byte of a memory word (most significant 8 bits).
ASCII (bits 11-13):
These three bits give the sign representation used for ASCII format:
βββββββ¬ββββββββββββββββββββββββ
βbits β sign representation β
βββββββΌββββββββββββββββββββββββ€
β000 β embedded trailing β
β001 β separate trailing β
β010 β embedded leading β
β011 β separate leading β
β100 β unsigned β
βββββββ΄ββββββββββββββββββββββββ
Bit 13 also represents an unsigned number in BCD representation.
r (bit 10):
Rounding bit. If rounding is selected, one is added to the shifted operand when the least significant digit is lost during shift and the last digit shifted out of the field is 25.
r = 1: rounding on
r = 0: rounding off
decimal point (bits 5-9):
These bits give the position of the decimal point (0 to 31, positive or negative). Zero is the decimal place to the right of the least significant digit. The number must be less than the operand field length.
field length (bits 0-4):
These bits give the operand field length in nibbles (4-bit values) or bytes (8-bit values). BCD numbers are represented by 4 bits (1 nibble), so the field length will be in nibbles; an ASCII coded digit is represented by a byte and the field length will be in bytes.
Operands start at any byte address in memory.
The maximum field length is 32 nibbles/bytes.
Decimal operands:
Decimal operands occupy a maximum of eight 16-bit memory locations. Each operand consists of BCD coded numbers.
Decimal operands must be right adjusted so that the least significant digit and sign are in the last byte of the operand field.
Before any instruction is executed, the operands are read into the register file. The result of the instruction is written into memory.
All decimal instructions use two operands. The descriptors of each operand are held in separate registers:
First operand descriptor: A and D registers
Second operand descriptor: X and T registers
Decimal overflow:
Decimal overflow is caused by:
EITHER a carry from the most significant digit position in the result
OR an oversized result, where the second operand was larger than the first, causing the significant digits of the result to be lost.
Note: The field size alone does not indicate possible overflow.
Most decimal instructions are followed by an instruction or jump to a routine which takes care of overflow errors, known as an error return. A decimal instruction executed without error generation skips the error return and program execution continues at the second instruction after it.
BCD- Binary Coded Decimal
Decimal digits are represented in binary-coded decimal (BCD), sometimes known as packed decimal.
β The ND-110 instruction set uses only the codes 1100 for plus and 1101 for minus.
The maximum length of an operand is 31 decimal digits plus a sign nibble (4 bits), this occupies eight consecutive memory locations (eight 16-bit words).
ASCII coded decimal
ASCII-coded decimal notation uses eight bits to represent a decimal digit.
The format of an ASCII code decimal is:
βββββββββ¬ββββββββ
β zone β digit β
βββββββββ΄ββββββββ
When interrupt system off: halts the program and enters the operatorβs communication.
INTERRUPT CONTROL INSTRUCTIONS
These instructions are PRIVILEGED and only available to:
Programs running in system mode (rings 2-3)
Programs running without memory protection
These instructions control the CPU interrupt system.
General Description
The ND-110 has a priority interrupt system with 16 program levels.
Each program level has its own set of working registers (A, B, D, L, P, STS, T, X).
The program levels have increasing priority, that is, program level 15 has the highest priority and program level 0 the lowest.
The 16 levels are subdivided as follows:
level
used for
controlled by
15
very fast user interrupts
program/ext. device
14
internal hardware status interrupts
program/ext. device
13-10
vectored interrupts*
program/ext. device
9-0
system and user programs
program
*2048 possible sources
Program level selection and control
Program level selection and control is via two 16-bit registers:
PID: Priority Interrupt Detect
PIE: Priority Interrupt Enable
PID is affected by program and external interrupts; PIE is controlled by program only. They can only be changed or monitored by the privileged instructions: TRA, TRR, MST, and MCL (see pages 118-120).
Note:
When the power is turned on, the power-up sequence resets PIE and PID so that program level 0 is selected.
These instructions are PRIVILEGED and only available to:
Programs running in system mode (rings 2-3)
Programs running without memory protection
These instructions read/write from/to physical memory locations independent of whether paging is on or off. If the address is within the page-table range then the page tables are affected.
physical memory operation type (bits 15-6 and 2-0):
There are seven physical memory read/write instructions, specified by a base octal code of 143300β (bits 15-6) and type field (bits 2-0).
disp.: The contents of the T and X register give the effective address of the physical memory location (see page 28).
A 3-bit displacement can be added to the X register within the instruction code. This is denoted by Ξ in the following codes:
instruction mnemonic
octal code
LDATX
1433Ξ0
LDXTX
1433Ξ1
LDDTX
1433Ξ2
LDBTX
1433Ξ3
STATX
1433Ξ4
STZTX
1433Ξ5
STDTX
1433Ξ6
β If you use programs written for ND-100 computers with the microprogram version numbers 015xx A-J (48 bit) or 026xx A-F (32 bit), LDBTX would have been followed by a word containing 177777β.
This is not necessary for later ND-100 versions nor the ND-110. Running these earlier programs may change the status of the K bit in the ND-110 and later ND-100s.
**Values:** - `ZRO` (`0000`): Specificed bit equals zero - `ONE` (`0001`): Specified bit equals one - `BAC` (`0002`): Specified bit equals K - `BCM` (`0003`): Complement specified bit |
| `bit_no` | numeric | 7-3 | Specify bit number
**Values:** - `SSTG` (`000010`): Floating rounding flag - `SSK` (`000020`): 1-bit accumulator (K) - `SSZ` (`000030`): Error flag (Z) - `SSQ` (`000040`): Dynamic overflow flag (Q) - `SSO` (`000050`): Static overflow flag (O) - `SSC` (`000060`): Page table flag - `SSM` (`000070`): Page table flag |
#### π Examples
##### Reset the static overflow flag
```
BSET ZRO SSO
```
--------------------------------------------------------------------------------
### BSKP
#### β‘ Quick Reference
| Property | Value |
|:---------|:-------|
| Format | `BSKP ` |
| Category | Bit instructions |
| Privilege | User |
| Mask | `1111_1111_1000_0000` |
#### π Description
Skip next location if specified condition is true
P β΅ P+1
#### π Format
```
BSKP
```
#### Bit Layout
```
β 15 14 13 12 11β 10 9 8 7 β 7 6 5 4 3 β
βββββββββββββββββββββΌββββββββββββββββΌβββββββββββββββββββββββ€
β opcode β condition β bit_no β
βββββββββββββββββββββ΄ββββββββββββββββ΄βββββββββββββββββββββββ
```
#### π§ Operands
| Name | Type | Bits | Description |
|:-----|:-----|:-----|:------------|
| `opcode` | opcode | 15-11 | The opcode determines what type of operation occurs |
| `condition` | enum | 10-7 | Specify condition for BSKP and BSET
**Values:** - `ZRO` (`0000`): Specificed bit equals zero - `ONE` (`0001`): Specified bit equals one - `BAC` (`0002`): Specified bit equals K - `BCM` (`0003`): Complement specified bit |
| `bit_no` | numeric | 7-3 | Specify bit number
**Values:** - `SD` (`000010`): D register as source - `SP` (`000020`): P register as source - `SB` (`000030`): B register as source - `SL` (`000040`): L register as source - `SA` (`000050`): A register as source - `ST` (`000060`): T register as source - `SX` (`000070`): X register as source - `ZERO` (`000000`): Source value equals zero |
| `destination` | enum | 2-0 | Destination register (dr)
**Values:** - `STS` (`000000`): Status register - `DD` (`000001`): D register - `DP` (`000002`): P register - `DB` (`000003`): B register - `DL` (`000004`): L register - `DA` (`000005`): A register - `DT` (`000006`): T register - `DX` (`000007`): X register |
#### π Examples
##### Copy the program counter on program level 14 into the A register of the current program level.
```
```
--------------------------------------------------------------------------------
### IRW
#### β‘ Quick Reference
| Property | Value |
|:---------|:-------|
| Format | `IRW ` |
| Category | Inter-level Instructions |
| Privilege | Privileged |
| Mask | `1111_1111_1000_0000` |
#### π Description
Inter Register Write
Write A to specified register on specified level
#### π Format
```
IRW
```
#### Bit Layout
```
β 15 14 13 12 11 10 9 8 7 β 6 5 4 3 β 2 1 0 β
βββββββββββββββββββββββββββββββββββββΌββββββββββββββββΌβββββββββββββββ€
β opcode β level β register β
βββββββββββββββββββββββββββββββββββββ΄ββββββββββββββββ΄βββββββββββββββ
```
#### π§ Operands
| Name | Type | Bits | Description |
|:-----|:-----|:-----|:------------|
| `opcode` | opcode | 15-7 | The opcode for inter-register read |
| `level` | uint4 | 6-3 | Privilege level to access (0-15) |
| `register` | enum | 2-0 | Register to read from specified level
**Values:** - `STS` (`000000`): Status register - `DD` (`000001`): D register - `DP` (`000002`): P register - `DB` (`000003`): B register - `DL` (`000004`): L register - `DA` (`000005`): A register - `DT` (`000006`): T register - `DX` (`000007`): X register |
#### π Examples
##### Copy the A register on the current program level into the B register on program level 8
```
```
--------------------------------------------------------------------------------
### JAF
#### β‘ Quick Reference
| Property | Value |
|:---------|:-------|
| Format | ` JAF ` |
| Category | Sequencing Instructions |
| Privilege | User |
| Mask | `1111_1111_0000_0000` |
#### π Description
Condtion: Jump if (A) != 0 (jump if A filled)
#### π Detailed Information
If condition true, jump to the address of the program counter plus the value of displacement.
If condition false, continue program execution at (P) + 1.
'displacement' = The eight displacement (disp) bits give a signed range of -128 to 127 locations to be jumped if the condition is true.
#### π Format
```
JAF
```
#### Bit Layout
```
β 15 14 13 12 11 10 9 8 β 7 6 5 4 3 2 1 0 β
βββββββββββββββββββββββββββββββββΌββββββββββββββββββββββββββββββββββ€
β opcode β displacement β
βββββββββββββββββββββββββββββββββ΄ββββββββββββββββββββββββββββββββββ
```
#### π§ Operands
| Name | Type | Bits | Description |
|:-----|:-----|:-----|:------------|
| `opcode` | opcode | 15-8 | The opcode determines what type of operation occurs |
| `displacement` | displacement | 7-0 | 8-bit signed field gives the memory address displacement (2's complement notation giving a displacement range of -128 to 127 memory locations) |
--------------------------------------------------------------------------------
### JAN
#### β‘ Quick Reference
| Property | Value |
|:---------|:-------|
| Format | ` JAN ` |
| Category | Sequencing Instructions |
| Privilege | User |
| Mask | `1111_1111_0000_0000` |
#### π Description
Condtion: Jump if (A) < 0 (jump if A is negative)
#### π Detailed Information
If condition true, jump to the address of the program counter plus the value of displacement.
If condition false, continue program execution at (P) + 1.
'displacement' = The eight displacement (disp) bits give a signed range of -128 to 127 locations to be jumped if the condition is true.
#### π Format
```
JAN
```
#### Bit Layout
```
β 15 14 13 12 11 10 9 8 β 7 6 5 4 3 2 1 0 β
βββββββββββββββββββββββββββββββββΌββββββββββββββββββββββββββββββββββ€
β opcode β displacement β
βββββββββββββββββββββββββββββββββ΄ββββββββββββββββββββββββββββββββββ
```
#### π§ Operands
| Name | Type | Bits | Description |
|:-----|:-----|:-----|:------------|
| `opcode` | opcode | 15-8 | The opcode determines what type of operation occurs |
| `displacement` | displacement | 7-0 | 8-bit signed field gives the memory address displacement (2's complement notation giving a displacement range of -128 to 127 memory locations) |
--------------------------------------------------------------------------------
### JAP
#### β‘ Quick Reference
| Property | Value |
|:---------|:-------|
| Format | ` JAP ` |
| Category | Sequencing Instructions |
| Privilege | User |
| Mask | `1111_1111_0000_0000` |
#### π Description
Condtion: Jump if (A) > 0 (jump if A positive)
#### π Detailed Information
If condition true, jump to the address of the program counter plus the value of displacement.
If condition false, continue program execution at (P) + 1.
'displacement' = The eight displacement (disp) bits give a signed range of -128 to 127 locations to be jumped if the condition is true.
#### π Format
```
JAP
```
#### Bit Layout
```
β 15 14 13 12 11 10 9 8 β 7 6 5 4 3 2 1 0 β
βββββββββββββββββββββββββββββββββΌββββββββββββββββββββββββββββββββββ€
β opcode β displacement β
βββββββββββββββββββββββββββββββββ΄ββββββββββββββββββββββββββββββββββ
```
#### π§ Operands
| Name | Type | Bits | Description |
|:-----|:-----|:-----|:------------|
| `opcode` | opcode | 15-8 | The opcode determines what type of operation occurs |
| `displacement` | displacement | 7-0 | 8-bit signed field gives the memory address displacement (2's complement notation giving a displacement range of -128 to 127 memory locations) |
--------------------------------------------------------------------------------
### JAZ
#### β‘ Quick Reference
| Property | Value |
|:---------|:-------|
| Format | ` JAZ ` |
| Category | Sequencing Instructions |
| Privilege | User |
| Mask | `1111_1111_0000_0000` |
#### π Description
Condtion: Jump if (A) == 0 (jump if A is zero)
#### π Detailed Information
If condition true, jump to the address of the program counter plus the value of displacement.
If condition false, continue program execution at (P) + 1.
'displacement' = The eight displacement (disp) bits give a signed range of -128 to 127 locations to be jumped if the condition is true.
#### π Format
```
JAZ
```
#### Bit Layout
```
β 15 14 13 12 11 10 9 8 β 7 6 5 4 3 2 1 0 β
βββββββββββββββββββββββββββββββββΌββββββββββββββββββββββββββββββββββ€
β opcode β displacement β
βββββββββββββββββββββββββββββββββ΄ββββββββββββββββββββββββββββββββββ
```
#### π§ Operands
| Name | Type | Bits | Description |
|:-----|:-----|:-----|:------------|
| `opcode` | opcode | 15-8 | The opcode determines what type of operation occurs |
| `displacement` | displacement | 7-0 | 8-bit signed field gives the memory address displacement (2's complement notation giving a displacement range of -128 to 127 memory locations) |
--------------------------------------------------------------------------------
### JMP
#### β‘ Quick Reference
| Property | Value |
|:---------|:-------|
| Format | `JMP ` |
| Category | Sequencing Instructions |
| Privilege | User |
#### π Description
Jump - Unconditional jump to specified address
The next instruction is taken from the effective address of the JMP instruction(the effective address is ioaded into the program counter).
#### π Format
```
JMP
```
#### Bit Layout
```
β 15 14 13 12 11β 10 9 8 β 7 6 5 4 3 2 1 0 β
β β X I B β β
βββββββββββββββββββββΌβββββββββββββββββββΌβββββββββββββββββββββββββββββββββββ€
β opcode β addressing_mode β displacement β
βββββββββββββββββββββ΄βββββββββββββββββββ΄βββββββββββββββββββββββββββββββββββ
```
> **Note:** This instruction uses addressing modes. See [Addressing Modes](#addressing-modes) for details.
#### π§ Operands
| Name | Type | Bits | Description |
|:-----|:-----|:-----|:------------|
| `opcode` | opcode | 15-11 | The opcode determines what type of operation occurs |
| `addressing_mode` | addressing_modes | 10-8 | These three bits give the addressing mode for the instruction |
| `displacement` | displacement | 7-0 | 8-bit signed field gives the memory address displacement (2's complement notation giving a displacement range of -128 to 127 memory locations) |
--------------------------------------------------------------------------------
### JNC
#### β‘ Quick Reference
| Property | Value |
|:---------|:-------|
| Format | ` JNC ` |
| Category | Sequencing Instructions |
| Privilege | User |
| Mask | `1111_1111_0000_0000` |
#### π Description
Increment X and jump if X is negative
#### π Detailed Information
X = X + 1
Condtion: Jump if (X) < 0 (jump if X is negative)
If condition true, jump to the address of the program counter plus the value of displacement.
If condition false, continue program execution at (P) + 1.
'displacement' = The eight displacement (disp) bits give a signed range of -128 to 127 locations to be jumped if the condition is true.
#### π Format
```
JNC
```
#### Bit Layout
```
β 15 14 13 12 11 10 9 8 β 7 6 5 4 3 2 1 0 β
βββββββββββββββββββββββββββββββββΌββββββββββββββββββββββββββββββββββ€
β opcode β displacement β
βββββββββββββββββββββββββββββββββ΄ββββββββββββββββββββββββββββββββββ
```
#### π§ Operands
| Name | Type | Bits | Description |
|:-----|:-----|:-----|:------------|
| `opcode` | opcode | 15-8 | The opcode determines what type of operation occurs |
| `displacement` | displacement | 7-0 | 8-bit signed field gives the memory address displacement (2's complement notation giving a displacement range of -128 to 127 memory locations) |
--------------------------------------------------------------------------------
### JPC
#### β‘ Quick Reference
| Property | Value |
|:---------|:-------|
| Format | ` JPC ` |
| Category | Sequencing Instructions |
| Privilege | User |
| Mask | `1111_1111_0000_0000` |
#### π Description
Increment X and jump if X is positive
#### π Detailed Information
X = X + 1
Condtion: Jump if (X) > 0 (jump if X is positive)
If condition true, jump to the address of the program counter plus the value of displacement.
If condition false, continue program execution at (P) + 1.
'displacement' = The eight displacement (disp) bits give a signed range of -128 to 127 locations to be jumped if the condition is true.
#### π Format
```
JPC
```
#### Bit Layout
```
β 15 14 13 12 11 10 9 8 β 7 6 5 4 3 2 1 0 β
βββββββββββββββββββββββββββββββββΌββββββββββββββββββββββββββββββββββ€
β opcode β displacement β
βββββββββββββββββββββββββββββββββ΄ββββββββββββββββββββββββββββββββββ
```
#### π§ Operands
| Name | Type | Bits | Description |
|:-----|:-----|:-----|:------------|
| `opcode` | opcode | 15-8 | The opcode determines what type of operation occurs |
| `displacement` | displacement | 7-0 | 8-bit signed field gives the memory address displacement (2's complement notation giving a displacement range of -128 to 127 memory locations) |
--------------------------------------------------------------------------------
### JPL
#### β‘ Quick Reference
| Property | Value |
|:---------|:-------|
| Format | `JPL ` |
| Category | Sequencing Instructions |
| Privilege | User |
#### π Description
Jump if Plus - Jump to specified address if the result of the last operation was positive (sign bit is 0)
The contents of the program counter are transferred to the L register and the next instruction is taken from the effective address of the JPL instruction.
Note that the L register points to the instruction after the jump(the program counter incremented before transfer to the L register).
#### π Format
```
JPL
```
#### Bit Layout
```
β 15 14 13 12 11β 10 9 8 β 7 6 5 4 3 2 1 0 β
β β X I B β β
βββββββββββββββββββββΌβββββββββββββββββββΌβββββββββββββββββββββββββββββββββββ€
β opcode β addressing_mode β displacement β
βββββββββββββββββββββ΄βββββββββββββββββββ΄βββββββββββββββββββββββββββββββββββ
```
> **Note:** This instruction uses addressing modes. See [Addressing Modes](#addressing-modes) for details.
#### π§ Operands
| Name | Type | Bits | Description |
|:-----|:-----|:-----|:------------|
| `opcode` | opcode | 15-11 | The opcode determines what type of operation occurs |
| `addressing_mode` | addressing_modes | 10-8 | These three bits give the addressing mode for the instruction |
| `displacement` | displacement | 7-0 | 8-bit signed field gives the memory address displacement (2's complement notation giving a displacement range of -128 to 127 memory locations) |
--------------------------------------------------------------------------------
### JXN
#### β‘ Quick Reference
| Property | Value |
|:---------|:-------|
| Format | ` JXN ` |
| Category | Sequencing Instructions |
| Privilege | User |
| Mask | `1111_1111_0000_0000` |
#### π Description
Condtion: Jump if (X) < 0 (jump if X negative)
#### π Detailed Information
If condition true, jump to the address of the program counter plus the value of displacement.
If condition false, continue program execution at (P) + 1.
'displacement' = The eight displacement (disp) bits give a signed range of -128 to 127 locations to be jumped if the condition is true.
#### π Format
```
JXN
```
#### Bit Layout
```
β 15 14 13 12 11 10 9 8 β 7 6 5 4 3 2 1 0 β
βββββββββββββββββββββββββββββββββΌββββββββββββββββββββββββββββββββββ€
β opcode β displacement β
βββββββββββββββββββββββββββββββββ΄ββββββββββββββββββββββββββββββββββ
```
#### π§ Operands
| Name | Type | Bits | Description |
|:-----|:-----|:-----|:------------|
| `opcode` | opcode | 15-8 | The opcode determines what type of operation occurs |
| `displacement` | displacement | 7-0 | 8-bit signed field gives the memory address displacement (2's complement notation giving a displacement range of -128 to 127 memory locations) |
--------------------------------------------------------------------------------
### JXZ
#### β‘ Quick Reference
| Property | Value |
|:---------|:-------|
| Format | ` JXZ ` |
| Category | Sequencing Instructions |
| Privilege | User |
| Mask | `1111_1111_0000_0000` |
#### π Description
Condtion: Jump if (X) == 0 (jump if X is zero)
#### π Detailed Information
If condition true, jump to the address of the program counter plus the value of displacement.
If condition false, continue program execution at (P) + 1.
'displacement' = The eight displacement (disp) bits give a signed range of -128 to 127 locations to be jumped if the condition is true.
#### π Format
```
JXZ
```
#### Bit Layout
```
β 15 14 13 12 11 10 9 8 β 7 6 5 4 3 2 1 0 β
βββββββββββββββββββββββββββββββββΌββββββββββββββββββββββββββββββββββ€
β opcode β displacement β
βββββββββββββββββββββββββββββββββ΄ββββββββββββββββββββββββββββββββββ
```
#### π§ Operands
| Name | Type | Bits | Description |
|:-----|:-----|:-----|:------------|
| `opcode` | opcode | 15-8 | The opcode determines what type of operation occurs |
| `displacement` | displacement | 7-0 | 8-bit signed field gives the memory address displacement (2's complement notation giving a displacement range of -128 to 127 memory locations) |
--------------------------------------------------------------------------------
### LACB
#### β‘ Quick Reference
| Property | Value |
|:---------|:-------|
| Format | `LACB ` |
| Category | Control Instructions |
| Privilege | Privileged |
| Mask | `1111_1111_1100_0111` |
#### π Description
Load the A register from the core map-table bank (CMBNK).
(A) <--- (ea)
ea = (B) + Ξ = CMBNK entry
Ξ: 3-bit displacement added to B included in the instruction opcode (bits 5-3)
#### π Format
```
LACB
```
#### Bit Layout
```
β 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 β
ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ€
β opcode β
ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ
```
--------------------------------------------------------------------------------
### LASB
#### β‘ Quick Reference
| Property | Value |
|:---------|:-------|
| Format | `LASB ` |
| Category | Control Instructions |
| Privilege | Privileged |
| Mask | `1111_1111_1100_0111` |
#### π Description
Load the A register with the contents of the segment-table bank (STBNK).
(A) <--- (ea)
ea = (B) + Ξ = STBNK entry
Ξ: 3-bit displacement added to B included in the instruction opcode (bits 5-3)
#### π Format
```
LASB
```
#### Bit Layout
```
β 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 β
ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ€
β opcode β
ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ
```
--------------------------------------------------------------------------------
### LBIT
#### β‘ Quick Reference
| Property | Value |
|:---------|:-------|
| Format | `LBIT` |
| Category | Control Instructions |
| Privilege | Privileged |
| Mask | `1111_1111_1111_1111` |
#### π Description
Load single bit accumulator (K) with logical memory bit.
(X) points to the start of a bit array
(A) points to the bit within the array
#### π Format
```
LBIT
```
#### Bit Layout
```
β 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 β
ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ€
β opcode β
ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ
```
#### π§ Operands
| Name | Type | Bits | Description |
|:-----|:-----|:-----|:------------|
| `opcode` | opcode | 15-0 | The opcode determines what type of operation occurs |
--------------------------------------------------------------------------------
### LBITP
#### β‘ Quick Reference
| Property | Value |
|:---------|:-------|
| Format | `LBITP` |
| Category | Control Instructions |
| Privilege | Privileged |
| Mask | `1111_1111_1111_1111` |
#### π Description
Load single bit accumulator (K) with physical memory bit.
(T) points to the bank number containing the bit array
(X) points to the start of a bit array
(A) points to the bit within the array
#### π Format
```
LBITP
```
#### Bit Layout
```
β 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 β
ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ€
β opcode β
ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ
```
#### π§ Operands
| Name | Type | Bits | Description |
|:-----|:-----|:-----|:------------|
| `opcode` | opcode | 15-0 | The opcode determines what type of operation occurs |
--------------------------------------------------------------------------------
### LBYT
#### β‘ Quick Reference
| Property | Value |
|:---------|:-------|
| Format | `LBYT` |
| Category | Byte Instructions |
| Privilege | User |
| Mask | `1111_1111_1111_1111` |
#### π Description
Load byte from memory to A register
Addressing: EL = (T) + (X)/2
- If least significant bit of X = 1: Load right byte
- If least significant bit of X = 0: Load left byte
Load the byte addressed by the contents of the T and X register into the lower byte of the A register. The higher byte of the A register is cleared.
The contents of T point to the beginning of a character string and the contents of X to a byte within the string.
#### π Format
```
LBYT
```
#### Bit Layout
```
β 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 β
ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ€
β opcode β
ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ
```
#### π§ Operands
| Name | Type | Bits | Description |
|:-----|:-----|:-----|:------------|
| `opcode` | opcode | 15-0 | The opcode determines what type of operation occurs |
--------------------------------------------------------------------------------
### LBYTP
#### β‘ Quick Reference
| Property | Value |
|:---------|:-------|
| Format | `LBYTP` |
| Category | Control Instructions |
| Privilege | Privileged |
| Mask | `1111_1111_1111_1111` |
#### π Description
Load the A register with a byte from physical memory.
(D) points to the bank number containing the byte array
(T) points to the start of a byte array
(X) points to the actual byte within the array
#### π Format
```
LBYTP
```
#### Bit Layout
```
β 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 β
ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ€
β opcode β
ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ
```
#### π§ Operands
| Name | Type | Bits | Description |
|:-----|:-----|:-----|:------------|
| `opcode` | opcode | 15-0 | The opcode determines what type of operation occurs |
--------------------------------------------------------------------------------
### LDA
#### β‘ Quick Reference
| Property | Value |
|:---------|:-------|
| Format | `LDA ` |
| Category | Memory Transfer - Load Instruction |
| Privilege | User |
| Mask | `1111_1000_0000_0000` |
#### π Description
Load A register
Load the contents of the memory location pointed to by the effective address into the A register.
#### π Format
```
LDA
```
#### Bit Layout
```
β 15 14 13 12 11β 10 9 8 β 7 6 5 4 3 2 1 0 β
β β X I B β β
βββββββββββββββββββββΌβββββββββββββββββββΌβββββββββββββββββββββββββββββββββββ€
β opcode β addressing_mode β displacement β
βββββββββββββββββββββ΄βββββββββββββββββββ΄βββββββββββββββββββββββββββββββββββ
```
> **Note:** This instruction uses addressing modes. See [Addressing Modes](#addressing-modes) for details.
#### π§ Operands
| Name | Type | Bits | Description |
|:-----|:-----|:-----|:------------|
| `opcode` | opcode | 15-11 | The opcode determines what type of operation occurs |
| `addressing_mode` | addressing_modes | 10-8 | These three bits give the addressing mode for the instruction |
| `displacement` | displacement | 7-0 | 8-bit signed field gives the memory address displacement (2's complement notation giving a displacement range of -128 to 127 memory locations) |
--------------------------------------------------------------------------------
### LDATX
#### β‘ Quick Reference
| Property | Value |
|:---------|:-------|
| Format | `LDATX ` |
| Category | Memory Transfer Instructions |
| Privilege | Privileged |
| Mask | `1111_1111_1100_0111` |
#### π Description
Load A register
(A) β΅ (ea)
Load the contents of the physical memory location pointed to by the effective address into the A register.
#### π Format
```
LDATX
```
#### Bit Layout
```
β 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 β
ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ€
β opcode β
ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ
```
--------------------------------------------------------------------------------
### LDBTX
#### β‘ Quick Reference
| Property | Value |
|:---------|:-------|
| Format | `LDBTX ` |
| Category | Memory Transfer Instructions |
| Privilege | Privileged |
| Mask | `1111_1111_1100_0111` |
#### π Description
Load B register
(B) β΅ 177000β OR (2(ea))
Load the contents of the physical memory location pointed to by twice the effective address contents into the B register, then OR the value with 177000β.
See description for usage.
#### π Format
```
LDBTX
```
#### Bit Layout
```
β 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 β
ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ€
β opcode β
ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ
```
--------------------------------------------------------------------------------
### LDD
#### β‘ Quick Reference
| Property | Value |
|:---------|:-------|
| Format | `LDD ` |
| Category | Memory Transfer - Double word instructions |
| Privilege | User |
| Mask | `1111_1000_0000_0000` |
#### π Description
Load double word
A β΅ (ea)
D β΅ (ea) + 1
Load the contents of the memory location pointed to by the effective address into the A register
Load the contents of the memory location pointed to by the effective address plus one into the D register.
#### π Format
```
LDD
```
#### Bit Layout
```
β 15 14 13 12 11β 10 9 8 β 7 6 5 4 3 2 1 0 β
β β X I B β β
βββββββββββββββββββββΌβββββββββββββββββββΌβββββββββββββββββββββββββββββββββββ€
β opcode β addressing_mode β displacement β
βββββββββββββββββββββ΄βββββββββββββββββββ΄βββββββββββββββββββββββββββββββββββ
```
> **Note:** This instruction uses addressing modes. See [Addressing Modes](#addressing-modes) for details.
#### π§ Operands
| Name | Type | Bits | Description |
|:-----|:-----|:-----|:------------|
| `opcode` | opcode | 15-11 | The opcode determines what type of operation occurs |
| `addressing_mode` | addressing_modes | 10-8 | These three bits give the addressing mode for the instruction |
| `displacement` | displacement | 7-0 | 8-bit signed field gives the memory address displacement (2's complement notation giving a displacement range of -128 to 127 memory locations) |
--------------------------------------------------------------------------------
### LDDTX
#### β‘ Quick Reference
| Property | Value |
|:---------|:-------|
| Format | `LDDTX ` |
| Category | Memory Transfer Instructions |
| Privilege | Privileged |
| Mask | `1111_1111_1100_0111` |
#### π Description
Load double word
(A) β΅ (ea)
(D) β΅ (ea + 1)
Load the contents of the physical memory location pointed to by the effective address into the A register and the contents of the effective address plus one into the D register.
#### π Format
```
LDDTX
```
#### Bit Layout
```
β 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 β
ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ€
β opcode β
ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ
```
--------------------------------------------------------------------------------
### LDF
#### β‘ Quick Reference
| Property | Value |
|:---------|:-------|
| Format | `LDF ` |
| Category | Standard Floating Instructions |
| Privilege | User |
| Mask | `1111_1000_0000_0000` |
#### π Description
Load floating accumulator (TAD) from memory (FW)
Memory format:
(T) β΅ EL
(A) β΅ EL+1
(D) β΅ EL+2
Load the contents of the memory location pointed to by the effective address into the T register, the contents of the effective address plus one into the A register and the contents of the effective address plus two into the D register.
#### π Format
```
LDF
```
#### Bit Layout
```
β 15 14 13 12 11β 10 9 8 β 7 6 5 4 3 2 1 0 β
β β X I B β β
βββββββββββββββββββββΌβββββββββββββββββββΌβββββββββββββββββββββββββββββββββββ€
β opcode β addressing_mode β displacement β
βββββββββββββββββββββ΄βββββββββββββββββββ΄βββββββββββββββββββββββββββββββββββ
```
> **Note:** This instruction uses addressing modes. See [Addressing Modes](#addressing-modes) for details.
#### π§ Operands
| Name | Type | Bits | Description |
|:-----|:-----|:-----|:------------|
| `opcode` | opcode | 15-11 | The opcode determines what type of operation occurs |
| `addressing_mode` | addressing_modes | 10-8 | These three bits give the addressing mode for the instruction |
| `displacement` | displacement | 7-0 | 8-bit signed field gives the memory address displacement (2's complement notation giving a displacement range of -128 to 127 memory locations) |
--------------------------------------------------------------------------------
### LDT
#### β‘ Quick Reference
| Property | Value |
|:---------|:-------|
| Format | `LDT ` |
| Category | Memory Transfer - Load Instruction |
| Privilege | User |
| Mask | `1111_1000_0000_0000` |
#### π Description
Load T register
(T) β΅ (ea)
Load the contents of the memory location pointed to by the effective address into the T register.
#### π Format
```
LDT
```
#### Bit Layout
```
β 15 14 13 12 11β 10 9 8 β 7 6 5 4 3 2 1 0 β
β β X I B β β
βββββββββββββββββββββΌβββββββββββββββββββΌβββββββββββββββββββββββββββββββββββ€
β opcode β addressing_mode β displacement β
βββββββββββββββββββββ΄βββββββββββββββββββ΄βββββββββββββββββββββββββββββββββββ
```
> **Note:** This instruction uses addressing modes. See [Addressing Modes](#addressing-modes) for details.
#### π§ Operands
| Name | Type | Bits | Description |
|:-----|:-----|:-----|:------------|
| `opcode` | opcode | 15-11 | The opcode determines what type of operation occurs |
| `addressing_mode` | addressing_modes | 10-8 | These three bits give the addressing mode for the instruction |
| `displacement` | displacement | 7-0 | 8-bit signed field gives the memory address displacement (2's complement notation giving a displacement range of -128 to 127 memory locations) |
--------------------------------------------------------------------------------
### LDX
#### β‘ Quick Reference
| Property | Value |
|:---------|:-------|
| Format | `LDX ` |
| Category | Memory Transfer - Load Instruction |
| Privilege | User |
| Mask | `1111_1000_0000_0000` |
#### π Description
Load X register
(X) β΅ (ea)
Load the contents of the memory location pointed to by the effective address into the X register.
#### π Format
```
LDX
```
#### Bit Layout
```
β 15 14 13 12 11β 10 9 8 β 7 6 5 4 3 2 1 0 β
β β X I B β β
βββββββββββββββββββββΌβββββββββββββββββββΌβββββββββββββββββββββββββββββββββββ€
β opcode β addressing_mode β displacement β
βββββββββββββββββββββ΄βββββββββββββββββββ΄βββββββββββββββββββββββββββββββββββ
```
> **Note:** This instruction uses addressing modes. See [Addressing Modes](#addressing-modes) for details.
#### π§ Operands
| Name | Type | Bits | Description |
|:-----|:-----|:-----|:------------|
| `opcode` | opcode | 15-11 | The opcode determines what type of operation occurs |
| `addressing_mode` | addressing_modes | 10-8 | These three bits give the addressing mode for the instruction |
| `displacement` | displacement | 7-0 | 8-bit signed field gives the memory address displacement (2's complement notation giving a displacement range of -128 to 127 memory locations) |
--------------------------------------------------------------------------------
### LDXTX
#### β‘ Quick Reference
| Property | Value |
|:---------|:-------|
| Format | `LDXTX ` |
| Category | Memory Transfer Instructions |
| Privilege | Privileged |
| Mask | `1111_1111_1100_0111` |
#### π Description
Load X register
(X) β΅ (ea)
Load the contents of the physical memory location pointed to by the effective address into the X register.
#### π Format
```
LDXTX
```
#### Bit Layout
```
β 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 β
ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ€
β opcode β
ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ
```
--------------------------------------------------------------------------------
### LEAVE
#### β‘ Quick Reference
| Property | Value |
|:---------|:-------|
| Format | `LEAVE` |
| Category | Stack Operations |
| Privilege | User |
| Mask | `1111_1111_1111_1111` |
#### π Description
Leave stack.
This instruction saves the previous stack pointer in LINK.
The B register is restored to its previous value (PREVB) and the stack is left by loading the P register (program counter) with the return address (LINK).
(P) β΅ (B = 200β) {LINK}
(B) β΅ (B = 177β) {PREVB}
Format:
LEAVE
#### π Format
```
LEAVE
```
#### Bit Layout
```
β 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 β
ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ€
β opcode β
ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ
```
#### π§ Operands
| Name | Type | Bits | Description |
|:-----|:-----|:-----|:------------|
| `opcode` | opcode | 15-0 | The opcode determines what type of operation occurs |
--------------------------------------------------------------------------------
### LRB
#### β‘ Quick Reference
| Property | Value |
|:---------|:-------|
| Format | `LRB ` |
| Category | Register Block Instructions |
| Privilege | Privileged |
| Mask | `1111_1111_1100_0000` |
#### π Description
Load register block
Load the contents of a memory block pointed to by the X register into the register block of the program level given in the instruction.
If the instruction specifies the current program level, the P register (program counter) is not loaded from memory and is unchanged.
#### π Detailed Information
The memory block pointed to by the X register is loaded into the register block for the specified program level. The mapping is as follows:
P (level N) β΅ (ea)
X (level N) β΅ (ea + 1)
T (level N) β΅ (ea + 2)
A (level N) β΅ (ea + 3)
D (level N) β΅ (ea + 4)
L (level N) β΅ (ea + 5)
STS (level N) β΅ (ea + 6)
B (level N) β΅ (ea + 7)
Where (ea) is the address in memory pointed to by the X register.
If the current program level is specified, the P register is not loaded and remains unchanged.
#### π Format
```
LRB
```
#### Bit Layout
```
β 15 14 13 12 11β 6 5 4 3 β 2 1 0 β
βββββββββββββββββββββΌββββββββββββββββΌβββββββββββββββ€
β opcode β level β type β
βββββββββββββββββββββ΄ββββββββββββββββ΄βββββββββββββββ
```
#### π§ Operands
| Name | Type | Bits | Description |
|:-----|:-----|:-----|:------------|
| `opcode` | opcode | 15-11 | The opcode determines what type of operation occurs |
| `level` | uint4 | 6-3 | The level to load the register block to |
| `type` | enum | 2-0 | The type of register block function
**Values:** - `SRB` (`0`): Store Register Block - `LRB` (`2`): Load Register Block |
#### π Examples
##### LRB 160β (152760β)
Load the memory block pointed to by the X register into the register on program level 14.
P (level 14) β΅ (ea)
X (level 14) β΅ (ea + 1)
β β
B (level 14) β΅ (ea + 7)
```
LRB 160
```
--------------------------------------------------------------------------------
### LWCS
#### β‘ Quick Reference
| Property | Value |
|:---------|:-------|
| Format | `LWCS` |
| Category | privileged |
| Privilege | Privileged |
| Mask | `1111_1111_1111_1111` |
#### π Description
Writable Control Store Instruction
This instruction is PRIVILEGED and only available to:
- programs running in system mode (rings 2-3)
- programs running without memory protection
LWCS is a no-operation in the ND-110.
The ND-110 is software compatible but not microcode compatible and writing to the writable control store has no meaning in the ND-110.
A no-operation is executed so that programs written for the ND-100 and NORD-10 can continue.
Unused areas of the microprogram can be read or written to using the TRR CS or TRA CS instruction.
Further information on the LWCS instruction for the ND-100 can be found in the ND-100 Reference Manual (ND-06.014).
#### π Format
```
LWCS
```
#### Bit Layout
```
β 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 β
ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ€
β opcode β
ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ
```
#### π§ Operands
| Name | Type | Bits | Description |
|:-----|:-----|:-----|:------------|
| `opcode` | opcode | 15-0 | The opcode determines what type of operation occurs |
--------------------------------------------------------------------------------
### LXCB
#### β‘ Quick Reference
| Property | Value |
|:---------|:-------|
| Format | `LXCB ` |
| Category | Control Instructions |
| Privilege | Privileged |
| Mask | `1111_1111_1100_0111` |
#### π Description
Load the X register from the core table bank (CMBNK).
(X) <--- (ea)
ea = (B) + Ξ = CMBNK entry
Ξ: 3-bit displacement added to B included in the instruction opcode (bits 5-3)
#### π Format
```
LXCB
```
#### Bit Layout
```
β 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 β
ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ€
β opcode β
ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ
```
--------------------------------------------------------------------------------
### LXSB
#### β‘ Quick Reference
| Property | Value |
|:---------|:-------|
| Format | `LXSB ` |
| Category | Control Instructions |
| Privilege | Privileged |
| Mask | `1111_1111_1100_0111` |
#### π Description
Load the X register from the segment table bank (STBNK).
(X) <--- (ea)
ea = (B) + Ξ = STBNK entry
Ξ: 3-bit displacement added to B included in the instruction opcode (bits 5-3)
#### π Format
```
LXSB
```
#### Bit Layout
```
β 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 β
ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ€
β opcode β
ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ
```
--------------------------------------------------------------------------------
### MCL
#### β‘ Quick Reference
| Property | Value |
|:---------|:-------|
| Format | `MCL ` |
| Category | Register Transfer |
| Privilege | Privileged |
| Mask | `1111_1111_1111_0000` |
#### π Description
Masked clear
The A register is used as a mask to clear bits within the selected internal register.
Setting a bit in the A register clears the corresponding bit in the internal register.
See table for internal registers that allow MCL.
#### π Format
```
MCL
```
#### Bit Layout
```
β 15 14 13 12 11 10 9 8 7 6 5 4 β 3 2 1 0 β
βββββββββββββββββββββββββββββββββββββββββββββββββΌβββββββββββββββββββββββ€
β opcode β internal_register β
βββββββββββββββββββββββββββββββββββββββββββββββββ΄βββββββββββββββββββββββ
```
#### π§ Operands
| Name | Type | Bits | Description |
|:-----|:-----|:-----|:------------|
| `opcode` | opcode | 15-4 | The opcode determines what type of operation occurs |
| `internal_register` | enum | 3-0 | The CPU internal register
**Values:** - `STS` (`0001`): - `PID` (`0006`): - `PIE` (`0007`): |
--------------------------------------------------------------------------------
### NLZ
#### β‘ Quick Reference
| Property | Value |
|:---------|:-------|
| Format | `NLZ ` |
| Category | Floating Conversion (Standard Format) |
| Privilege | User |
| Mask | `1111_1111_0000_0000` |
#### π Description
Normalize
Convert the number in A to a floating number in TAD
#### π Detailed Information
The number in the A register is converted to its floating point equivalent in the floating point accumulator (A and D registers),
using the scaling factor given, For integers, a scaling factor of +16 will give a floating point number with the same value as the integer.
The larger the scaling factor, the larger the Ploating point number.
The D register will be cleared when using single precision fixed point numbers.
Comments on 48-bit floating point CP
For the ND-110, 48-bit floating point CPU option, a further register (T) and memory location fea + 2) are used. In this case, the T register is linked to location ea, A to ea + 1 and D to ea + 2.
How to test for a 32-bit or 48-bit floating point CPU:
SAT 0
SAA 1
NLZ 20
This tests whether T is changed, if so, the CPU is 48-bit; otherwise it is 32-bit.
#### π Format
```
NLZ
```
#### Bit Layout
```
β 15 14 13 12 11 10 9 8 β 7 6 5 4 3 2 1 0 β
βββββββββββββββββββββββββββββββββΌββββββββββββββββββββββββββββββββββ€
β opcode β scaling_factor β
βββββββββββββββββββββββββββββββββ΄ββββββββββββββββββββββββββββββββββ
```
#### π§ Operands
| Name | Type | Bits | Description |
|:-----|:-----|:-----|:------------|
| `opcode` | opcode | 15-8 | The opcode for floating conversion |
| `scaling_factor` | numeric | 7-0 | Scaling factor in range -128 to 127 (gives converting range from 10^-39 to 10^39) |
#### π Examples
##### Convert the number in A to a floating number in TAD
```
NLZ
```
##### Integer to floating conversation
```
NLZ +20
```
--------------------------------------------------------------------------------
### OPCOM
#### β‘ Quick Reference
| Property | Value |
|:---------|:-------|
| Format | `OPCOM` |
| Category | Interrupt Control Instructions |
| Privilege | Privileged |
| Mask | `1111_1111_1111_1111` |
#### π Description
Operator Communication
This instruction is PRIVILEGED and only available to:
- programs running in system mode (rings 2-3)
- programs running without memory protection
This instruction allows the programmer to use a terminal in direct communication with the CPU board.
When the CPU is running, MOPC can be used to read input from the console.
This is the software equivalent to pressing the OPCOM button on the control panel of the ND-110.
#### π Format
```
OPCOM
```
#### Bit Layout
```
β 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 β
ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ€
β opcode β
ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ
```
#### π§ Operands
| Name | Type | Bits | Description |
|:-----|:-----|:-----|:------------|
| `opcode` | opcode | 15-0 | The opcode determines what type of operation occurs |
--------------------------------------------------------------------------------
### ORA
#### β‘ Quick Reference
| Property | Value |
|:---------|:-------|
| Format | `ORA ` |
| Category | Arithmetic and Logical |
| Privilege | User |
| Mask | `1111_1000_0000_0000` |
#### π Description
Logical inclusive OR to A register
A β΅ A | (EA)
Perform a bitwise OR operation between the contents of the A register and the contents of the memory location pointed to by the effective address, leaving the result in A.
#### π Format
```
ORA
```
#### Bit Layout
```
β 15 14 13 12 11β 10 9 8 β 7 6 5 4 3 2 1 0 β
β β X I B β β
βββββββββββββββββββββΌβββββββββββββββββββΌβββββββββββββββββββββββββββββββββββ€
β opcode β addressing_mode β displacement β
βββββββββββββββββββββ΄βββββββββββββββββββ΄βββββββββββββββββββββββββββββββββββ
```
> **Note:** This instruction uses addressing modes. See [Addressing Modes](#addressing-modes) for details.
#### π§ Operands
| Name | Type | Bits | Description |
|:-----|:-----|:-----|:------------|
| `opcode` | opcode | 15-11 | The opcode determines what type of operation occurs |
| `addressing_mode` | addressing_modes | 10-8 | These three bits give the addressing mode for the instruction |
| `displacement` | displacement | 7-0 | 8-bit signed field gives the memory address displacement (2's complement notation giving a displacement range of -128 to 127 memory locations) |
--------------------------------------------------------------------------------
### PACK
#### β‘ Quick Reference
| Property | Value |
|:---------|:-------|
| Format | `PACK` |
| Category | Decimal Instructions |
| Privilege | User |
| Mask | `1111_1111_1111_1111` |
#### π Description
Convert to BCD.
(op2) β΅ (op1) in BCD format
Convert the first operand from its ASCII format to BCD format, placing the result in the second operand location.
**Conversion process:**
PACK carries out the following steps:
1. Checks the sign and digits of the operand (op1) are encoded as ASCII digits. (Reporting illegal codes as error code 2.)
2. Takes the 4 least significant bits of each ASCII digit as the equivalent BCD digit.
3. Converts the ASCII sign of the operand to BCD:
ASCII BCD Sign
53β 14β +
55β 15β -
Note: If bit 13 of the descriptor D2 is set, then the code 17β (BCD unsigned) is used.
4. Extends the second operand field (op2) with zeros if the result is too small to fill the field.
Reports overflow has occurred (error code 3) if the second operand field length is too short to contain the significant digits of the result (the remaining digits are ignored).
**Error code:**
An error code is placed in bits 0 to 4 of the D register if an illegal code conversion is attempted or if overflow occurs. The first detected error will be reported.
Error code: 2 illegal codeβ
3 overflow
β bit 15 of both the A and D registers point to the byte containing the illegal code.
#### π Format
```
PACK
```
#### Bit Layout
```
β 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 β
ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ€
β opcode β
ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ
```
#### π§ Operands
| Name | Type | Bits | Description |
|:-----|:-----|:-----|:------------|
| `opcode` | opcode | 15-0 | The opcode determines what type of operation occurs |
--------------------------------------------------------------------------------
### PIOF
#### β‘ Quick Reference
| Property | Value |
|:---------|:-------|
| Format | `PIOF` |
| Category | Memory Management Instructions |
| Privilege | Privileged |
| Mask | `1111_1111_1111_1111` |
#### π Description
Memory management and interrupt system OFF
Disables both the memory management and interrupt systems. This combines the functions of the IOF and POF instructions.
Before_use:
Check conditions of the IOF instruction.
#### π Format
```
PIOF
```
#### Bit Layout
```
β 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 β
ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ€
β opcode β
ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ
```
#### π§ Operands
| Name | Type | Bits | Description |
|:-----|:-----|:-----|:------------|
| `opcode` | opcode | 15-0 | The opcode determines what type of operation occurs |
--------------------------------------------------------------------------------
### PION
#### β‘ Quick Reference
| Property | Value |
|:---------|:-------|
| Format | `PION` |
| Category | Memory Management Instructions |
| Privilege | User |
| Mask | `1111_1111_1111_1111` |
#### π Description
Memory management and interrupt system ON
Enable both the memory management and interrupt systems. This combines the functions of the ION and PON instructions.
#### π Format
```
PION
```
#### Bit Layout
```
β 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 β
ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ€
β opcode β
ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ
```
#### π§ Operands
| Name | Type | Bits | Description |
|:-----|:-----|:-----|:------------|
| `opcode` | opcode | 15-0 | The opcode determines what type of operation occurs |
--------------------------------------------------------------------------------
### POF
#### β‘ Quick Reference
| Property | Value |
|:---------|:-------|
| Format | `POF` |
| Category | Interrupt Control Instructions |
| Privilege | Privileged |
| Mask | `1111_1111_1111_1111` |
#### π Description
Memory management OFF
Disable memory management system. The next instruction will be taken from a physical address given by the address following the POF instruction.
Note: The CPU will be in an unrestricted mode without any hardware protection features - all instructions are legal and all memory accessible.
#### π Format
```
POF
```
#### Bit Layout
```
β 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 β
ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ€
β opcode β
ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ
```
#### π§ Operands
| Name | Type | Bits | Description |
|:-----|:-----|:-----|:------------|
| `opcode` | opcode | 15-0 | The opcode determines what type of operation occurs |
--------------------------------------------------------------------------------
### PON
#### β‘ Quick Reference
| Property | Value |
|:---------|:-------|
| Format | `PON` |
| Category | Memory Management Instructions |
| Privilege | User |
| Mask | `1111_1111_1111_1111` |
#### π Description
Memory management ON
Enable memory management system. The next instruction after PON will then use the pageindex table specified by PCR.
BEFORE USE ENSURE:
- Interrupt system is enabled,
- Internal hardware interrupts are enabled,
- Page tables and PCR registers are initialized.
#### π Format
```
PON
```
#### Bit Layout
```
β 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 β
ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ€
β opcode β
ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ
```
#### π§ Operands
| Name | Type | Bits | Description |
|:-----|:-----|:-----|:------------|
| `opcode` | opcode | 15-0 | The opcode determines what type of operation occurs |
--------------------------------------------------------------------------------
### RADD
#### β‘ Quick Reference
| Property | Value |
|:---------|:-------|
| Format | `RADD [sub-instruction(s)] ` |
| Category | Register Operations |
| Privilege | User |
| Mask | `1111_1100_0000_0000` |
#### π Description
Add source to destination (dr): = (dr) + (sr)
#### π Detailed Information
These instructions specify operations between source (sr) and destination (dr) registers.
Optional sub-instructions:
- **CLD**: CLD=1. Zero is used instead of the destination register as an operand (dr register contents are unchanged).
- **CM1**: CM1=1. The 1's complement of the source register is used as an operand (sr register contents are unchanged).
- **ADC**: This mnemonic represents C=0 I=1. Add previous carry to destination register.
- **AD1**: This mnemonic represents C=1 I=0. Add 1 to destination register.
- **CM2**: This compound sub-instruction is equivalent to CM1 ADC.
Flags affected:
RADD instructions affect the carry (C) and overflow (O and Q) flags as follows:
- **C = 1**: If a carry occurs from the signed bit positions of the adder.
- **O = 1 ; Q = 1**: If an overflow occurs, that is if the signs of the two operands are equal and the sign of the result is different.
- **O = 1 ; Q = 0**: If overflow does not exist, the dynamic overflow flag (O) is reset while the static overflow flag (Q) is left unchanged.
---
### Instruction combinations
COPY
RADD dr β΅ dr + sr
RADD CLD dr β΅ sr β‘ COPY
RADD CM1 dr β΅ dr + ~sr
RADD CM1 CLD dr β΅ ~sr
RADD AD1 dr β΅ dr + sr + 1
RADD CLD AD1 dr β΅ sr + 1
RADD CM1 AD1 dr β΅ dr - sr β‘ RSUB
RADD CM1 CLD AD1 dr β΅ -sr
RADD ADC dr β΅ dr + sr + c
RADD CLD ADC dr β΅ sr + c
RADD CM1 ADC dr β΅ dr + ~sr + c
RADD CM1 CLD ADC dr β΅ ~sr + c
RINC
RADD AD1 is equivalent to RINC , increment dr register by one.
RDCR
RADD CM1 is equivalent to RDCR , decrement dr register by one.
RCLR
RADD CLD 0 (COPY 0) is equivalent to RCLR , register clear.
EXIT
RADD CM1 SL DP (COPY SL DP) is equivalent to EXIT, return from subroutine.
#### π Format
```
RADD [sub-instruction(s)]
```
#### Bit Layout
```
β 15 14 13 12 11β 10 β 9 β 8 β 8 7 β 7 β 6 β 5 4 3 β 2 1 0 β
βββββββββββββββββββββΌβββββββΌβββββββΌβββββββΌββββββββΌβββββββΌβββββββΌββββββββββββΌββββββββββββββββββββββββ€
β opcode β rad β ADC β AD1 β CM2 β CM1 β CLD β source β destination β
βββββββββββββββββββββ΄βββββββ΄βββββββ΄βββββββ΄ββββββββ΄βββββββ΄βββββββ΄ββββββββββββ΄ββββββββββββββββββββββββ
```
#### π§ Operands
| Name | Type | Bits | Description |
|:-----|:-----|:-----|:------------|
| `opcode` | opcode | 15-11 | The opcode for register inclusive OR |
| `rad` | constant | 10 | Arithmetic operation flag |
| `ADC` | flag | 9 | Also addd old carry to destination |
| `AD1` | flag | 8 | Also add one to destination |
| `CM1` | flag | 7 | Use one's complement of source |
| `CM2` | flag | 8-7 | Two's complement (CM1 AD1) |
| `CLD` | flag | 6 | Clear destination before operation |
| `source` | enum | 5-3 | Source register (sr)
**Values:** - `SD` (`000010`): D register as source - `SP` (`000020`): P register as source - `SB` (`000030`): B register as source - `SL` (`000040`): L register as source - `SA` (`000050`): A register as source - `ST` (`000060`): T register as source - `SX` (`000070`): X register as source - `ZERO` (`000000`): Source value equals zero |
| `destination` | enum | 2-0 | Destination register (dr)
**Values:** - `SD` (`000010`): D register as source - `SP` (`000020`): P register as source - `SB` (`000030`): B register as source - `SL` (`000040`): L register as source - `SA` (`000050`): A register as source - `ST` (`000060`): T register as source - `SX` (`000070`): X register as source - `ZERO` (`000000`): Source value equals zero |
| `destination` | enum | 2-0 | Destination register (dr)
**Values:** - `DD` (`000001`): D register as destination - `DP` (`000002`): P register as destination - `DB` (`000003`): B register as destination - `DL` (`000004`): L register as destination - `DA` (`000005`): A register as destination - `DT` (`000006`): T register as destination - `DX` (`000007`): X register as destination |
#### π Examples
##### AND the contents of the L and X registers. Store the result in the X register. (144447β)
```
RAND SL DX
```
##### AND the contents of the T and B registers, taking the 1's complement of the sr as the source operand. (144663β)
Result in B.
```
RAND CM1 ST DB
```
--------------------------------------------------------------------------------
### RCLR
#### β‘ Quick Reference
| Property | Value |
|:---------|:-------|
| Format | `RCLR ` |
| Category | Register Operations |
| Privilege | User |
| Mask | `1111_1111_1111_1000` |
#### π Description
Register clear
#### π Detailed Information
RCLR is a compound mnemonic for "COPY 0" (or RADD CLD 0).
#### π Format
```
RCLR
```
#### Bit Layout
```
β 15 14 13 12 11 10 9 8 7 6 5 4 β 2 1 0 β
βββββββββββββββββββββββββββββββββββββββββββββββββΌβββββββββββββββββ€
β opcode β destination β
βββββββββββββββββββββββββββββββββββββββββββββββββ΄βββββββββββββββββ
```
#### π§ Operands
| Name | Type | Bits | Description |
|:-----|:-----|:-----|:------------|
| `opcode` | opcode | 15-4 | The opcode for register arithmetic |
| `destination` | enum | 2-0 | Destination register (dr)
**Values:** - `SD` (`000010`): D register as source - `SP` (`000020`): P register as source - `SB` (`000030`): B register as source - `SL` (`000040`): L register as source - `SA` (`000050`): A register as source - `ST` (`000060`): T register as source - `SX` (`000070`): X register as source - `ZERO` (`000000`): Source value equals zero |
| `destination` | enum | 2-0 | Destination register (dr)
**Values:** - `SD` (`000010`): D register as source - `SP` (`000020`): P register as source - `SB` (`000030`): B register as source - `SL` (`000040`): L register as source - `SA` (`000050`): A register as source - `ST` (`000060`): T register as source - `SX` (`000070`): X register as source - `ZERO` (`000000`): Source value equals zero |
| `destination` | enum | 2-0 | Destination register (dr)
**Values:** - `DD` (`000001`): D register as destination - `DP` (`000002`): P register as destination - `DB` (`000003`): B register as destination - `DL` (`000004`): L register as destination - `DA` (`000005`): A register as destination - `DT` (`000006`): T register as destination - `DX` (`000007`): X register as destination |
#### π Examples
##### Exclusive OR the contents of the B and Y registers, leaving the result in B
```
REXO ST DB
```
--------------------------------------------------------------------------------
### RGLOB
#### β‘ Quick Reference
| Property | Value |
|:---------|:-------|
| Format | `RGLOB` |
| Category | Control Instructions |
| Privilege | Privileged |
| Mask | `1111_1111_1111_1111` |
#### π Description
Examine global pointers.
(T) <--- bank number of segment table (STBNK)
(A) <--- start address within bank (STSRT)
(D) <--- bank number of core map table (CMBNK)
#### π Format
```
RGLOB
```
#### Bit Layout
```
β 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 β
ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ€
β opcode β
ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ
```
#### π§ Operands
| Name | Type | Bits | Description |
|:-----|:-----|:-----|:------------|
| `opcode` | opcode | 15-0 | The opcode determines what type of operation occurs |
--------------------------------------------------------------------------------
### RINC
#### β‘ Quick Reference
| Property | Value |
|:---------|:-------|
| Format | `RINC ` |
| Category | Register Operations |
| Privilege | User |
| Mask | `1111_1111_1111_1000` |
#### π Description
Register increment
dr β΅ dr + 1
RINC is a compound mnemonic for RADD AD1.
#### π Format
```
RINC
```
#### Bit Layout
```
β 15 14 13 12 11 10 9 8 7 6 5 4 β 2 1 0 β
βββββββββββββββββββββββββββββββββββββββββββββββββΌβββββββββββββββββ€
β opcode β destination β
βββββββββββββββββββββββββββββββββββββββββββββββββ΄βββββββββββββββββ
```
#### π§ Operands
| Name | Type | Bits | Description |
|:-----|:-----|:-----|:------------|
| `opcode` | opcode | 15-4 | The opcode for register arithmetic |
| `destination` | enum | 2-0 | Destination register (dr)
**Values:** - `SD` (`000010`): D register as source - `SP` (`000020`): P register as source - `SB` (`000030`): B register as source - `SL` (`000040`): L register as source - `SA` (`000050`): A register as source - `ST` (`000060`): T register as source - `SX` (`000070`): X register as source - `ZERO` (`000000`): Source value equals zero |
| `destination` | enum | 2-0 | Destination register (dr)
**Values:** - `SD` (`000010`): D register as source - `SP` (`000020`): P register as source - `SB` (`000030`): B register as source - `SL` (`000040`): L register as source - `SA` (`000050`): A register as source - `ST` (`000060`): T register as source - `SX` (`000070`): X register as source - `ZERO` (`000000`): Source value equals zero |
| `destination` | enum | 2-0 | Destination register (dr)
**Values:** - `SD` (`000010`): D register as source - `SP` (`000020`): P register as source - `SB` (`000030`): B register as source - `SL` (`000040`): L register as source - `SA` (`000050`): A register as source - `ST` (`000060`): T register as source - `SX` (`000070`): X register as source - `ZERO` (`000000`): Source value equals zero |
| `destination` | enum | 2-0 | Destination register (dr)