in-progress

ND-120 in FPGA

ND-120 in FPGA project screenshot

Recreating the ND-120 CPU at hardware level using the original design documents from 1988. Implemented in Verilog with Logisim Evolution for design and Verilator for testing. CPU/Decoder Gate Arrays and CPU Board are completed, with OPCOM communication functional.

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Mar 10, 2024Last Updated
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Technical Deep-Dive

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Features

  • fpga
  • verilog
  • norsk data
  • hardware
  • nd 120

Documentation

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